AT90PWM2 datasheet(17/365 Pages) ATMEL

17 / 365 page

AT90PWM2/3

4317B–AVR–02/05

Figure 8 shows the parallel instruction fetches and instruction executions enabled by the

Harvard architecture and the fast-access Register File concept. This is the basic pipelin-

ing concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks, and functions per power-unit.

Figure 8. The Parallel Instruction Fetches and Instruction Executions

Figure 9 shows the internal timing concept for the Register File. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 9. Single Cycle ALU Operation

Reset and Interrupt

Handling

The AVR provides several different interrupt sources. These interrupts and the separate

Reset Vector each have a separate program vector in the program memory space. All

interrupts are assigned individual enable bits which must be written logic one together

with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

Depending on the Program Counter value, interrupts may be automatically disabled

when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software

security. See the section “Memory Programming” on page 287 for details.

The lowest addresses in the program memory space are by default defined as the Reset

and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 56.

The list also determines the priority levels of the different interrupts. The lower the

address the higher is the priority level. RESET has the highest priority, and next is PSC2

CAPT – the PSC2 Capture Event. The Interrupt Vectors can be moved to the start of the

Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR).

Refer to “Interrupts” on page 56 for more information. The Reset Vector can also be

moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see

“Boot Loader Support – Read-While-Write Self-Programming” on page 273.

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

clk

CPU

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