ATMEGA640 datasheet(21/436 Pages) MICROCHIP

21 / 436 page

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the exter-

nal data SRAM is accessed using the same instructions as for the internal data memory access. When the internal

data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access

cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM.

This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If

the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cycles extra

because the three-byte program counter is pushed and popped, and external memory access does not take

advantage of the internal pipe-line memory access. When external SRAM interface is used with wait-state, one-

byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respec-

tively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the

instruction set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indi-

rect with Pre-decrement, and Indirect with Post-increment. In the Register file, registers R26 to R31 feature the

indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y-register

or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address

registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O registers, and the 4,196/8,192 bytes of internal data SRAM in the

ATmega640/1280/1281/2560/2561 are all accessible through all these addressing modes. The Register File is

described in “General Purpose Register File” on page 13.

ATMEGA640 데이터시트(PDF) 21 Page - Microchip Technology