ATMEGA640 datasheet(16/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

7.6.1

RAMPZ – Extended Z-pointer Register for ELPM/SPM

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note

that LPM is not affected by the RAMPZ setting.

Figure 7-4.

The Z-pointer used by ELPM and SPM

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.

For compatibility with future devices, be sure to write these bits to zero.

7.6.2

EIND – Extended Indirect Register

For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and

ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the EIND setting.

Figure 7-5.

The Indirect-pointer used by EICALL and EIJMP

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.

For compatibility with future devices, be sure to write these bits to zero.

7.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the

CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 7-6 on page 17 shows the parallel instruction fetches and instruction executions enabled by the Harvard

architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS

per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per

power-unit.

Bit

76543

0x3B (0x5B)

RAMPZ7

RAMPZ6

RAMPZ5

RAMPZ4

RAMPZ3

RAMPZ2

RAMPZ1

RAMPZ0

RAMPZ

Read/Write

R/W

Initial Value

00000

Bit

(Individually)

RAMPZ

Bit (Z-pointer)

Bit

765

432

0x3C (0x5C)

EIND7

EIND6

EIND5

EIND4

EIND3

EIND2

EIND1

EIND0

EIND

Read/Write

R/W

Initial Value

Bit

(Individually)

EIND

Bit

(Indirect-

pointer)

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