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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATMEGA640 데이터시트(PDF) 156 Page - Microchip Technology |
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ATMEGA640 데이터시트(HTML) 156 Page - Microchip Technology |
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156 / 436 page  156 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A Note: A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1//COMnC1 is set. See “Phase Correct PWM Mode” on page 148. for more details. 17.11.5 TCCR1B – Timer/Counter 1 Control Register B 17.11.6 TCCR3B – Timer/Counter 3 Control Register B 17.11.7 TCCR4B – Timer/Counter 4 Control Register B 17.11.8 TCCR5B – Timer/Counter 5 Control Register B • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its output. The input capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICESn: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Reg- ister (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input capture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. • Bit 4:3 – WGMn3:2: Waveform Generation Mode Bit 765 4 3 210 (0x81) ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 765 4 3 210 (0x91) ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 210 (0xA1) ICNC4 ICES4 – WGM43 WGM42 CS42 CS41 CS40 TCCR4B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 210 (0x121) ICNC5 ICES5 – WGM53 WGM52 CS52 CS51 CS50 TCCR5B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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