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ATMEGA640 데이터시트(PDF) 165 Page - Microchip Technology |
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ATMEGA640 데이터시트(HTML) 165 Page - Microchip Technology |
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165 / 436 page ![]() 165 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sam- pling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is rec- ommended that maximum frequency of an external clock source is less than fclk_I/O/2.5. An external clock source can not be prescaled. Figure 18-2. Prescaler for synchronous Timer/Counters PSR10 Clear Tn Tn clk I/O Synchronization Synchronization TIMER/COUNTERn CLOCK SOURCE clk Tn TIMER/COUNTERn CLOCK SOURCE clk Tn CSn0 CSn1 CSn2 CSn0 CSn1 CSn2 |
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