68HC705JB4 datasheet(73/134 Pages) FREESCALE

73 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

UNIVERSAL SERIAL BUS MODULE

MOTOROLA

REV 2

10-7

Figure 10-7. CRC Block Diagram for Data Packets

10.2.1.6 End Of Packet (EOP)

The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The

single-ended 0 state is indicated by both D+ and D– being below 0.8 V. EOP will

be signaled by driving D+ and D– to the single-ended 0 state for two bit times

followed by driving the lines to the idle state for one bit time. The transition from

the single-ended 0 to the idle state deﬁnes the end of the packet. The idle state is

asserted for one bit time and then both the D+ and D– output drivers are placed in

their high-impedance state. The bus termination resistors hold the bus in the idle

state. Figure 10-8 shows the data signaling and voltage levels for an end of

packet transaction.

MUX

next bit

Input / Output

- Update every bit time

- Reset to ones at SOP

Equal?

Good CRC

Bad CRC

Expected Residual:

Generator Polynomial:

Data Stream

Output

Data Stream

CRC16 Transmitted

MSB first after final

data byte.

TRANSMIT

RECEIVE

00 0 0 0

10 0 0 0

00 0 1 0 1

00 0 0 0

1 0 000

0 0 110 1

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705JB4 데이터시트(PDF) 73 Page - Freescale Semiconductor, Inc

68HC705JB4 데이터시트(HTML) 73 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL