68HC705JB4 datasheet(89/134 Pages) FREESCALE

89 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

UNIVERSAL SERIAL BUS MODULE

MOTOROLA

REV 2

10-23

T1SEQ — Endpoint1/Endpoint 2 Transmit Sequence Bit

This read/write bit determines which type of data packet (DATA0 or DATA1) will

be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2.

Toggling of this bit must be controlled by software. Reset clears this bit.

1 =

DATA1 Token active for next Endpoint 1/Endpoint 2 transmit

0 =

DATA0 Token active for next Endpoint 1/Endpoint 2 transmit

ENDADD — Endpoint Address Select

This

read/write

bit

speciﬁes

whether

the

data

inside

the

registers

UE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a

successful Endpoint 2 USB response to a hosts IN token are satisﬁed

(TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit

is conﬁgured for Endpoint 1, the USB responds with a NAK handshake packet.

1 =

The data buffers are used for Endpoint 2

0 =

The data buffers are used for Endpoint 1

TX1E — Endpoint 1/Endpoint 2 Transmit Enable

This read/write bit enables a transmit to occur when the USB Host controller

sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint

enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set.

Software should set the TX1E bit when data is ready to be transmitted. It must

be cleared by software when no more data needs to be transmitted.

If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake

to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit.

1 =

Data is ready to be sent.

0 =

Data is not ready. Respond with NAK.

FRESUM — Force Resume

This read/write bit forces a resume state (“K” or non-idle state) onto the USB

data lines to initiate a remote wake-up. Software should control the timing of the

forced resume to be between 10ms and 15 ms. Setting this bit will not cause

the RESUMF bit to set.

1 =

Force data lines to “K” state

0 =

Default

TP1SIZ3-TP1SIZ0 — Endpoint 1/Endpoint 2 Transmit Data Packet Size

These read/write bits store the number of transmit data bytes for the next IN

token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset.

10.5.6 USB Control Register 2 (UCR2)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

UCR2

TX1ST

ENABLE2 ENABLE1

STALL2

STALL1

$0037

TX1STR

reset

0000

= Unimplemented

Figure 10-25. USB Control Register 2 (UCR2)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705JB4 데이터시트(PDF) 89 Page - Freescale Semiconductor, Inc

68HC705JB4 데이터시트(HTML) 89 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL