68HC705JB4 datasheet(9/134 Pages) FREESCALE

9 / 134 page

February 24, 1999

GENERAL RELEASE SPECIFICATION

MC68HC05JB4

MOTOROLA

REV 2

vii

LIST OF FIGURES

Figure

Title

Page

1-1

MC68HC05JB4 Block Diagram........................................................................ 1-3

1-2

MC68HC05JB4 Pin Assignment ...................................................................... 1-4

1-3

Oscillator Connections ..................................................................................... 1-5

2-1

MC68HC05JB4 Memory Map .......................................................................... 2-1

2-2

MC68HC05JB4 I/O Registers $0000-$000F.................................................... 2-3

2-3

MC68HC05JB4 I/O Registers $0010-$001F.................................................... 2-4

2-4

MC68HC05JB4 I/O Registers $0020-$002F.................................................... 2-5

2-5

MC68HC05JB4 I/O Registers $0030-$003F.................................................... 2-6

2-6

COP Register (COPR) ..................................................................................... 2-6

3-1

MC68HC05 Programming Model ..................................................................... 3-1

4-1

Interrupt Stacking Order................................................................................... 4-2

4-2

Interrupt Flowchart ........................................................................................... 4-3

4-3

External Interrupt (IRQ) Logic .......................................................................... 4-5

4-4

External Interrupt (IRQ2) Logic ........................................................................ 4-6

4-5

IRQ Control and Status Register (ICSR)......................................................... 4-6

5-1

Reset Sources.................................................................................................. 5-1

5-2

COP Watchdog Register (COPR) ................................................................... 5-3

6-1

STOP and WAIT Flowchart.............................................................................. 6-2

7-1

Slow Falling-edge Output Driver ...................................................................... 7-1

8-1

Multi-Function Timer Block Diagram ................................................................ 8-1

8-2

Timer Counter Register.................................................................................... 8-3

8-3

Timer Control/Status Register (TCSR)............................................................. 8-3

9-1

Programmable Timer Block Diagram ............................................................... 9-1

9-2

Programmable Timer Counter Block Diagram ................................................. 9-2

9-3

Programmable Timer Counter Registers (TMRH, TMRL)................................ 9-3

9-4

Alternate Counter Block Diagram..................................................................... 9-4

9-5

Alternate Counter Registers (ACRH, ACRL).................................................... 9-4

9-6

Timer Input Capture Block Diagram................................................................. 9-5

9-7

Input Capture Registers (ICRH, ICRL)............................................................. 9-6

9-8

Timer Output Compare Block Diagram ............................................................ 9-7

9-9

Output Compare Registers (OCRH, OCRL) .................................................... 9-7

9-10

Timer Control Register (TCR) .......................................................................... 9-8

9-11

Timer Status Registers (TSR) .......................................................................... 9-9

10-1

USB Block Diagram ....................................................................................... 10-2

10-2

Supported Transaction Types per Endpoint................................................... 10-3

10-3

Supported USB Packet Types ....................................................................... 10-4

10-4

Sync Pattern................................................................................................... 10-4

10-5

SOP, Sync Signaling and Voltage Levels ...................................................... 10-5

10-6

CRC Block Diagram for Address and Endpoint Fields................................... 10-6

10-7

CRC Block Diagram for Data Packets ........................................................... 10-7

10-8

EOP Transaction Voltage Levels ................................................................... 10-8

10-9

EOP Width Timing.......................................................................................... 10-8

10-10 External Low Speed Device Configuration................................................... 10-10

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705JB4 데이터시트(PDF) 9 Page - Freescale Semiconductor, Inc

68HC705JB4 데이터시트(HTML) 9 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL