DS31256 datasheet(133/183 Pages) MAXIM

133 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

133 of 183

10.1.3 PCI Bus Arbitration

The PCI bus can be arbitrated as shown in Figure 10-4. The initiator requests bus access by asserting

PREQ. A central arbiter grants the access some time later by asserting PGNT. Once the bus has been

granted, the initiator waits until both

PIRDY and PFRAME are deasserted (i.e., an idle cycle) before

acquiring the bus and beginning the transaction. As shown in Figure 10-3, the bus was still being used

when it was granted and the device had to wait until clock cycle #6 before it acquired the bus and began

the transaction. The arbiter can deassert

PGNT at any time and the initiator must relinquish the bus after

the current transfer is complete, which can be limited by the latency timer.

Figure 10-4. PCI Bus Arbitration Signaling Protocol

10.1.4 PCI Initiator Abort

If a target fails to respond to an initiator by asserting

PDEVSEL and PTRDY within 5 clock cycles, then

the initiator aborts the transaction by deasserting

PFRAME and then, one clock later, by deasserting

PIDRY (Figure 10-5). If such a scenario occurs, it is reported through the master abort status bit in the

PCI command/status configuration register (Section 10.2).

Figure 10-5. PCI Initiator Abort

123456

789

PCLK

PREQ

PGNT

PFRAME

Bus is Relinquished

Bus is Acquired

Wait for

PGNT Asserted

and then

PFRAME and

PIRDY Deasserted

123456789

PCLK

PFRAME

PIRDY

PTRDY

PDEVSEL

DS31256 데이터시트(PDF) 133 Page - Maxim Integrated Products