MCIMX503CVM8B datasheet(92/136 Pages) NXP

92 / 136 page

i.MX50 Applications Processors for Consumer Products, Rev. 7

Electrical Characteristics

Freescale Semiconductor

4.9.9.2

SSI Receiver Timing with Internal Clock

Figure 52 depicts the SSI receiver internal clock timing and Table 67 lists the timing parameters for the

receiver timing with internal clock.

Figure 52. SSI Receiver Internal Clock Timing Diagram

Table 67. SSI Receiver Timing with Internal Clock

Parameter

Min

Max

Unit

Internal Clock Operation

SS1

(Tx/Rx) CK clock period

81.4

—

SS2

(Tx/Rx) CK clock high period

36.0

—

SS3

(Tx/Rx) CK clock rise time

—

6.0

SS4

(Tx/Rx) CK clock low period

36.0

—

SS5

(Tx/Rx) CK clock fall time

—

6.0

SS7

(Rx) CK high to FS (bl) high

—

15.0

SS9

(Rx) CK high to FS (bl) low

—

15.0

SS11

(Rx) CK high to FS (wl) high

—

15.0

SS13

(Rx) CK high to FS (wl) low

—

15.0

SS20

SRXD setup time before (Rx) CK low

10.0

—

SS21

SRXD hold time after (Rx) CK low

0.0

—

SS50

SS48

SS1

SS4

SS2

SS51

SS20

SS21

SS49

SS7

SS9

SS11

SS13

SS47

SS3

SS5

TXC

(Output)

TXFS (bl)

(Output)

TXFS (wl)

(Output)

RXD

(Input)

RXC

(Output)

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