MCIMX503CVM8B datasheet(97/136 Pages) NXP

97 / 136 page

Electrical Characteristics

i.MX50 Applications Processors for Consumer Products, Rev. 7

Freescale Semiconductor

NOTE

•

All the timings for the SSI are given for a non-inverted serial clock

polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync

(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have

been inverted, all the timing remains valid by inverting the clock signal

STCK/SRCK and/or the frame sync STFS/SRFS shown in both the

tables and figures.

•

All timings are on Audiomux Pads when SSI is being used for data

transfer.

•

Tx and Rx refer to the transmit and receive sections of the SSI.

•

The terms WL and BL refer to word length (WL) and bit length (BL).

•

For internal Frame Sync operation using external clock, the FS timing is

same as that of Tx Data (for example, during AC97 mode of operation).

4.9.10

UART I/O Configuration and Timing Parameters

The following sections describe the UART I/O configuration and timing parameters.

4.9.10.1

UART RS-232 I/O Configuration in Different Modes

Table 70 shows the UART I/O configuration based on which mode is enabled.

4.9.10.2

UART RS-232 Serial Mode Timing

The following sections describe the electrical information of the UART module in the RS-232 mode.

Table 70. UART I/O Configuration vs. Mode

Port

DTE Mode

DCE Mode

Direction

Description

Direction

Description

RTS

Output

RTS from DTE to DCE

Input

RTS from DTE to DCE

CTS

Input

CTS from DCE to DTE

Output

CTS from DCE to DTE

TXD_MUX

Input

Serial data from DCE to DTE

Output

Serial data from DCE to DTE

RXD_MUX

Output

Serial data from DTE to DCE

Input

Serial data from DTE to DCE

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