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STM32WB15CC 데이터시트(PDF) 32 Page - STMicroelectronics |
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STM32WB15CC 데이터시트(HTML) 32 Page - STMicroelectronics |
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32 / 127 page ![]() Functional overview STM32WB15CC 32/127 DS13258 Rev 4 3.7.6 Reset mode To improve the consumption under reset, the I/Os state under and after reset is “analog state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is deactivated when the reset source is internal. 3.8 VBAT operation The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers) from an external battery, an external supercapacitor, or from VDD when no external battery nor an external supercapacitor are present. One anti-tamper detection pin is available in VBAT mode. VBAT operation is automatically activated when VDD is not present. An internal VBAT battery charging circuit is embedded and can be activated when VDD is present. Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC alarm/events do not exit it from VBAT operation. 3.9 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU1 resources and, consequently, reducing power supply consumption. In addition, these hardware connections result in fast and predictable latency. Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run and Sleep, Stop 0 and Stop 1 modes. Table 8. STM32WB15CC CPU1 peripherals interconnect matrix Source Destination Action TIMx TIMx Timers synchronization or chaining Y Y Y Y - ADC1 Conversion triggers Y Y Y Y - DMA Memory to memory transfer trigger Y Y Y Y - COMP1 Comparator output blanking Y Y Y Y - COMPx TIM1 TIM2 Timer input channel, trigger, break from analog signals comparison Y YYY - LPTIMERx Low-power timer triggered by analog signals comparison Y YYY Y ADC1 TIM1 Timer triggered by analog watchdog Y Y Y Y - RTC LPTIMERx Low-power timer triggered by RTC alarms or tampers Y YYY Y |
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