FAM65CR51AXZ2 datasheet(5/14 Pages) ONSEMI

5 / 14 page

FAM65CR51AXZ1, FAM65CR51AXZ2

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Table 4. ABSOLUTE MAXIMUM RATINGS OF THE BOOST DIODE (TJ = 25°C, Unless Otherwise Specified)

Symbol

Parameter

Rating

Unit

VRRM

Peak Repetitive Reverse Voltage (Note 4)

650

EAS

Avalanche Energy (17 A, 1 mH)

144

Continuous Rectified Forward Current, TC < 148_C

IF,MAX

Non−Repetitive Forward Surge Current, TC = 25_C, 10 ms

1100

IF,MAX

Non−Repetitive Forward Surge Current, TC = 150_C, 10 ms

1000

IFSM

Non−Repetitive Peak Surge Current (Sine Half Wave, Tp = 8.3 ms)

110

Power Dissipation (TC = 25_C)

166

Maximum Junction Temperature

−55 to +175

°C

Maximum Case Temperature

−40 to +125

°C

TSTG

Storage Temperature

−40 to +125

°C

4. VRRM and IF value referenced to TO220−2L Auto Qualified Package Device FFSP3065B_F085

Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE (TJ = 25°C, Unless Otherwise Specified)

Symbol

Parameter

Test Conditions

Min

Typ

Max

Unit

VDC

DC Blocking Voltage

IR = 200 mA

TC = 25°C

650

−

Instantaneous Forward Voltage

IF = 30 A

TC = 25°C

−

1.38

1.7

TC = 125°C

−

1.6

2.0

TC = 175°C

−

1.72

2.4

Instantaneous Reverse Current

VR = 650 V

TC = 25°C

−

0.5

TC = 125°C

−

1.0

TC = 175°C

−

2.0

160

Total Capacitive Charge

VR = 400 V

TC = 25°C

−

Total Capacitance

VR = 1 V

f = 100 kHz

1280

VR = 200 V

f = 100 kHz

139

VR = 400 V

f = 100 kHz

108

Table 6. THERMAL RESISTANCE

Parameters

Min

Typ

Max

Unit

RθJC (per MOSFET chip)

Q1,Q2 Thermal Resistance Junction−to−Case (Note 5)

−

0.19

0.27

°C/W

RθJS (per MOSFET chip)

Q1,Q2 Thermal Resistance Junction−to−Sink (Note 6)

−

0.61

−

°C/W

RθJC (per DIODE chip)

D1,D2 Thermal Resistance Junction−to−Case (Note 5)

−

0.7

0.9

°C/W

RθJS (per DIODE chip)

D1,D2 Thermal Resistance Junction−to−Sink (Note 6)

−

1.73

−

°C/W

5. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package

at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed

6. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal

interface material

Table 7. ISOLATION (Isolation resistance at tested voltage between the base plate and to control pins or power terminals.)

Test

Test Conditions

Isolation Resistance

Unit

Leakage @ Isolation Voltage (Hi−Pot)

VAC = 5 kV, 50 Hz

100M <

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