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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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WM8581 데이터시트(PDF) 29 Page - Wolfson Microelectronics plc |
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WM8581 데이터시트(HTML) 29 Page - Wolfson Microelectronics plc |
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29 / 94 page  Product Preview WM8581 w PP Rev 1.0 March 2006 29 4 SAIFLRP 0 In LJ/RJ/I 2S modes 0 = LRCLK not inverted 1 = LRCLK inverted In DSP Format: 0 = DSP Mode A 1 = DSP Mode B 5 SAIFBCP 0 SAIF BCLK polarity 0 = BCLK not inverted 1 = BCLK inverted 6 SAIF_EN 0 SAIF Enable 0 = SAIF disabled 1 = SAIF enabled Table 15 Audio Interface Control Notes 1. Right Justified mode does not support 32-bit data. If word length xAIFxxWL=11b in Right Justified mode, the word length is forced to 24 bits. In all modes, the data is signed 2's complement. The digital filters internal signal paths process 24-bit data. If the device is programmed to receive 16 or 20 bit data, the device pads the unused LSBs with zeros. If the device is programmed into 32 bit mode, the 8 LSBs are ignored. 2. In 24 bit I 2S mode, any data width of 24 bits or less is supported provided that LRCLK is high for a minimum of 24 BCLK cycles and low for a minimum of 24 BCLK cycles. If exactly 32 bit clocks occur in one full left/right clock period the interface will auto detect and configure a 16 bit data word length. |
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