DS0147 datasheet(66/128 Pages) MICROCHIP

66 / 128 page

Unit

VDD = 1.05 V

–1

VDD = 1.05 V

STD

VDD= 1.0 V –1

VDD= 1.0 V ST-

Bridging S-

ource

Total I/O B-

anks

Device

125

NNW

MPF500T

220

300

220

300

NNE

1. NNW source designates bridging that originates from the North West Corner or PIOs inside I/O bank 0

(the most western I/O bank at the north edge).

2. NNE source designates bridging that originates from the North East Corner or PIOs inside I/O bank 1

(the most eastern I/O bank at the north edge).

6.3.2

PLL

The following table describes PLL.

Table 74 • PLL Electrical Characteristics

Condition

Unit

Max

Typ

Min

Symbol

Parameter

MHz

1250

FINI

Input clock fre-

quency (integer

mode)

MHz

1250

FINF

Input clock fre-

quency (fraction-

al mode)

200

FINPULSE

Minimum refer-

ence or feed-

back pulse

width

MHz

312

FPHDETI

Frequency at

the Frequency

Phase Detector

(PFD) (integer

mode)

MHz

225

FPHDETF

Frequency at

the PFD (frac-

tional mode)

FINDUTY

Allowable input

duty cycle

1000

120

FMAXINJ

Maximum input

period clock jit-

ter (reference

and feedback

clocks)

MHz

5000

800

FVCO

PLL VCO fre-

quency

MHz

FPHDET/30

FPHDET/44

FPHDET/55

FBW

Loop bandwidth

(Int)

Microsemi Proprietary and Confidential. DS0147 Revision 1.0

AC Switching Characteristics

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