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CC1020-RTR1 데이터시트(PDF) 27 Page - Texas Instruments

부품명 CC1020-RTR1
상세설명  Single Chip Low Power RF Transceiver for Narrowband Systems
PDF  91 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

CC1020-RTR1 데이터시트(HTML) 27 Page - Texas Instruments

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CC1020
SWRS046
Page 27 of 92
DCLK is not used in transmit mode, and is
used as data output in receive mode. It can be
set to default high or low in transmit mode.
FSK modulating signal,
internal in CC1020
Data provided by UART (TXD)
Transmitter side:
DCLK is used as data output
provided by CC1020.
Connect to UART (RXD)
Demodulated signal (NRZ),
internal in CC1020
DIO is not used in receive mode. Used only
as data input in transmit mode
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side:
DCLK is not used in transmit mode, and is
used as data output in receive mode. It can be
set to default high or low in transmit mode.
FSK modulating signal,
internal in CC1020
Data provided by UART (TXD)
Transmitter side:
DCLK is used as data output
provided by CC1020.
Connect to UART (RXD)
Demodulated signal (NRZ),
internal in CC1020
DIO is not used in receive mode. Used only
as data input in transmit mode
DCLK
DIO
“RF”
“RF”
DCLK
DIO
Receiver side:
Figure 11. Transparent Asynchronous UART mode (SEP_DI_DO = 1)
Time
1
0 1 1 0 0 0 1 1 0 1
Tx
data
Time
1
0 1 1 0 0 0 1 1 0 1
Tx
data
Figure 12. Manchester encoding
10.
Data Rate Programming
The data rate (baud rate) is programmable
and depends on the crystal frequency and
the
programming
of
the
CLOCK
(CLOCK_A and CLOCK_B) registers.
The baud rate (B.R) is given by
2
1
)
1
_
(
8
.
.
DIV
DIV
DIV
REF
f
R
B
xosc
⋅
⋅
+
⋅
=
where DIV1 and DIV2 are given by the
value of MCLK_DIV1 and MCLK_DIV2.
Table 17 shows some possible data rates
as a function of crystal frequency in
synchronous
mode.
In
asynchronous
transparent UART mode any data rate up
to 153.6 kBaud can be used.
MCLK_DIV2[1:0]
DIV2
00
1
01
2
10
4
11
8
Table 15. DIV2 for different settings of
MCLK_DIV2
MCLK_DIV1[2:0]
DIV1
000
2.5
001
3
010
4
011
7.5
100
12.5
101
40
110
48
111
64
Table 16. DIV1 for different settings of
MCLK_DIV1



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