SPSB081C3 datasheet(24/135 Pages) STMICROELECTRONICS

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•

Multiple watchdog failures: FORCED_SLEEP_WD = 1 (15x watchdog failure)

•

Multiple thermal shutdowns 2: FORCED_SLEEP_TSD2/V1SC = 1 (7x TSD2)

•

V1 short at turn-on (V1 < V1fail for t > tv1short): FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

•

Loss of ground: SGNDLOSS(SR6) = 1

Table 10. Non recoverable failures conditions

Failure source

Failure condition

Diagnosis

Exit from fail-safe mode

Microcontroller

(oscillator)

15 consecutive

watchdog failures

FS (global status byte) =1

WDFAIL (SR 1) =1

FORCED_SLEEP_WD (SR 1) =1

Wake-up

TRIG=1 during long open

window Read&Clear SR1

Short at turn-on

FS (global status byte) =1

V1FAIL=1

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

Wake-up

Read&Clear SR1

Overvoltage

FS (global status byte) =1

FORCED_SLEEP_V1OV (SR2) =1

Wake-up

Read&Clear SR2

Temperature

7 times TSD2

FS (global status byte) =1

TW (SR 2) =1

TSD1 (SR 1) =1

TSD2 (SR 1) =1

FORCED_SLEEP_TSD2/V1SC (SR 1) = 1

Wake-up

Read&Clear SR1

SGND

Loss of ground at SGND

FS (global status byte) =1

SGNDLOSS (SR 6) = 1

Wake-up

Read&Clear SR6

3.8

Reset output (NRESET)

At power-up, the reset signal is low. When Vs>VPOR, the RSTB bit is set and SPI registers are set to default

values. If V1 is turned on and the voltage exceeds the V1 reset programmable threshold VRTx by SPI, the reset

output “NRESET” is pulled up by internal pull-up resistor to V1 voltage after a reset delay time (trd). This is

necessary for a defined start of the microcontroller when the application is switched on. As soon as the NRESET

is released, the watchdog timing starts with a long open window. At power down, the device is reset, and control

registers are set to default values and RSTB bit is set to “1” (see the following figure).

Figure 14. NReset pin

Data in

110 kΩ

Data out

GAPG1609151103CFT

A reset pulse is generated in case of:

•

V1 drops below VRTx (configurable by SPI) for t > tuv1

SPSB081

Reset output (NRESET)

DS14048 - Rev 1

page 24/135

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