SPSB081C5 datasheet(86/135 Pages) STMICROELECTRONICS

86 / 135 page

Bit

Name

Description

•

V1UV (when UV is more than 2ms)

•

TSD2

•

FORCED SLEEP TSD/V1SC

SR2(0x32)

•

FORCED SLEEP V1OV

SR6 (0x36):

•

SGNDLOSS

All control Registers are set to default

Control registers are blocked for WRITE access except the following bits:

CR1 (0x01):

•

TRIG

•

CAN_ACT

CR2 (0x02):

•

Timer settings (bits 8…13 and bits 16…21)

CR5 (0x05):

•

OUT1_x (bits 0…2)

•

OUT2_x (bits 4…6)

•

OUT3_x (bits 8…10)

•

OUT4_x (bits 12…14)

•

CR9 (0x09) to CR11 (0x0B) PWM frequency and duty cycles

Config register (0x3F)

•

V2_0

•

V2_1

0 = fail-safe inactive (default)

1 = fail-safe active

FS is cleared upon exit from fail-safe mode (refer to Section 3.7 Fail safe mode )

1. Individual failure flags may be masked in the CR1 (0x26).

2. Bit may be masked in the configuration register (0x3F), that is, the bit will not be included in the global status bit (GSB).

3. Open load status flags may be masked in the Configuration register (0x3F), i.e. the open load flag will be included in the FE

flag, but will not set the GSB. TW failure status flags may be masked in the Configuration register (0x3F), i.e. the TW flag

will be included in the GW flag, but will not set the GSB.

SPSB081

Global status byte (GSB)

DS14048 - Rev 1

page 86/135

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