L9945 datasheet(140/151 Pages) STMICROELECTRONICS

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6.7

Signal integrity check

For signal integrity purposes, the device offers the possibility of verifying the correct propagation and effects of the

control signals. The integrity of the output signals can be monitored via SPI issuing the following frames:

•

Frame 1 = 0xBAAAAAAA: channels 1 to 4 integrity report

•

Frame 2 = 0xCAAAAAAB: channels 5 to 8 integrity report

The response frame consists of 32 bit containing the following fields:

Table 51. Response frames to signal integrity requests

Response Frame

31-28

26-21

12-10

9-7

6-4

3-1

Frame issued

Fr1

1011

010101

PUPD4

PUPD3

PUPD2

PUPD1

Fr2

1100

010101

PUPD8

PUPD7

PUPD6

PUPD5

Note:

The SPI protocol is out of frame, meaning that the response to the current message will be issued on the

following frame.

Field description of Table 51 is listed below:

•

P: Parity bit, based on even parity calculation

•

PUPDx: Pull up / Pull down status. This field consists of 3 bit encoding the current status of the gate charge /

discharge current sources (IPU and IPD in Figure 12) for the xth channel. The code depends on the output

configuration:

High-Side with PFET

•

100 : IPD ON and IPU OFF→ transistor ON

•

010 : IPD OFF and IPU ON → transistor OFF

•

000 : IPD OFF and IPU OFF → output in three-state

•

Others : integrity of the output control is compromised

High-Side/Low-Side with NFET

•

010 : IPD ON and IPU OFF → transistor OFF

•

001 : IPD OFF and IPU ON → transistor ON

•

000: IPD OFF and IPU OFF → output in three-state

•

Others : integrity of the output control is compromised

•

Cx: Output control signal. This flag combines the control signals SPI_ON_OUTxx, NONx and

SPI_input_sel_xx to feedback if the xth channel is commanded ON or OFF

–

1 : output commanded ON

–

0 : output commanded OFF

•

Vx: Channel status. This flag provides feedback about the external FET output voltage (DRNx pin in case of

LS NMOS or HS PMOS, SNGPx pin in case of HS NMOS) through the internal diagnostic comparators

(refer to Section 6.4 for further information about diagnostics). The value of this bit depends on the channel

configuration:

High-Side with NFET/PFET

•

1 : Output voltage high (Vout > VOL) → transistor ON

•

0 : Output voltage low (Vout < VOL) → transistor OFF

Low-Side with NFET

•

1 : Drain voltage high (Vout > VLVT) → transistor OFF

•

0 : Drain voltage low (Vout < VLVT) → transistor ON

Note:

This information is not intended to replace diagnostics and must be used only to verify the control signal

integrity. Refer to Section 6.2 in order to understand how output diagnostic is performed and which are the

fault codes.

L9945

Signal integrity check

DS12275 - Rev 8

page 140/151

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