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VL53L7CX 데이터시트(PDF) 10 Page - STMicroelectronics |
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VL53L7CX 데이터시트(HTML) 10 Page - STMicroelectronics |
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10 / 40 page ![]() 2.3.1 Power up slew To ensure proper operation of the module, the following minimum slew rates on the supplies must be met for correct operation of the power on reset (POR) circuitry. The POR circuitry triggers at 0.9 V, but the supplies should reach their operation levels in accordance with the slew rates listed in the table below. Figure 9. Power up slew Note: The minimum reset time is the minimum time required for the device ROM to load and boot up after IOVDD reaches the POR rising threshold. The supply must have reached the minimum operating level (1.6 V) within this time. Note: The minimum slew rate on the IOVDD is the same regardless of 1.8 V or 2.8 V operation. Note: The AVDD rise time is determined by the internal analogue levels which must be stable for correct operation. Table 6. Supply slew rate minimum limits Supply status AVDD slew IOVDD slew Start together 0.001 V/µs 0.012 V/µs AVDD stable followed by IOVDD — 0.012 V/µs IOVDD stable followed by AVDD 0.001 V/µs — 2.3.2 Power up and I2C access For correct operation of the device, the I2C interface assumes the power level has reached 1.62 V. VL53L7CX Power up sequence DS13865 - Rev 3 page 10/40 |
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