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ORG4572-R01-TR2 데이터시트(PDF) 31 Page - List of Unclassifed Manufacturers

부품명 ORG4572-R01-TR2
상세설명  GNSS RECEIVER MODULE
PDF  40 Pages
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Multi Spider - ORG4572 Datasheet
Revision 3.0
November 23, 2014
20. DESIGN CONSIDERATIONS
20.1. ANTENNA
Antennas for GPS and GLONASS have a wider bandwidth than pure GPS antennas.
Some wideband antennas may not have a good axial ratio to block reflections of RHCP GPS and
GLONASS signals. These antennas have lower rejection of multipath reflections and tend to degrade
the overall performance of the receiver.
20.1.1. PASSIVE ANTENNA
Design with passive antenna requires RF layout skills and can be challenging.
20.1.2. ACTIVE ANTENNA
While designing with active antenna consider using WAKEUP output to control auxiliary DC bias.
20.2. RF
Multi Spider ORG4572 operates with received signal levels down to -167dBm and can be affected by
high absolute levels of RF signals, moderate levels of RF interference near the GNSS bands and by low-
levels of RF noise in the GNSS band.
RF interference from nearby electronic circuits or radio transmitters can contain enough energy to
desensitize ORG4572. These systems may also produce levels of energy outside of GNSS band, high
enough to leak through RF filters and degrade the operation of the radios in ORG4572.
This issue becomes more critical in small products, where there are industrial design constraints.
In that environment, transmitters for Wi-Fi, Bluetooth, RFID, cellular and other radios may have
antennas physically close to the GNSS receiver antenna.
To prevent degraded performance of ORG4572, OriginGPS recommends performing EMI/jamming
susceptibility tests for radiated and conducted noise on prototypes and assessing risks of other factors.
Contact OriginGPS for application specific recommendations and design review services.
21. OPERATION
When power is first applied, ORG4572 goes into a Hibernate state while integrated RTC starts and internal
Finite State Machine (FSM) sequences though to “Ready-to-Start” state.
Host is not required to control external master reset since module’s internal reset circuitry handles detection
of power application.
While in “Ready-to-Start” state, ORG4572 awaits a pulse to the ON_OFF input.
Since integrated RTC startup times are variable, host is required either to wait for a fixed interval or to
monitor a short Low-High-Low pulse on WAKEUP output that indicates FSM “Ready-to-Start” state.
Another option is to repeat a pulse on the ON_OFF input every second until the module starts by either
detecting a stable logic high level on WAKEUP output or neither generation of UART messages.



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