ORG4572-R01-TR2 datasheet(12/40 Pages) ETC

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Multi Spider - ORG4572 Datasheet

Revision 3.0

November 23, 2014

AgilePMU

SMPS

LDO

Auxiliary Subsystem

RTC

Temperature ADC

Power Controller

BBRAM

Host Interface and GPIO

PLL

GNSS Radio

GNSS Engine

Measurement Subsystem

DSP

ROM

RAM

Navigation Subsystem

ARM® CPU

ROM

RAM

Host SPI

Host I

Host UART

FIGURE 2 – SiRFstarV™ 5e GNSS SoC BLOCK DIAGRAM

SiRFstarV™ 5e SoC includes the following units:

GNSS radio subsystem containing single input dual receive paths for concurrent GPS and GLONASS,

harmonic-reject double balanced mixer, fractional-N synthesizer, integrated self-calibrating filters,

IF VGA with AGC, high-sample rate ADCs with adaptive dynamic range.

Measurement subsystem including DSP core for GNSS signals acquisition and tracking, interference

scanner and detector, wideband and narrowband interference removers, multipath and cross-

correlation detectors, dedicated DSP code ROM and DSP cache RAM.

Measurement subsystem interfaces GNSS radio subsystem.

Navigation subsystem comprising ARM7® microprocessor system for position, velocity and time

solution, program ROM, data RAM, cache and patch RAM, MEMS sensor driver, SPI flash driver,

host interface UART, SPI and I²C drivers.

Navigation subsystem interfaces measurement subsystem.

Auxiliary subsystem containing RTC block and health monitor, temperature sensor for reference

clock compensation, battery-backed SRAM for satellite data storage, voltage supervisor with POR,

PLL controller, GPIO controller, 48-bit RTC timer and alarms, CPU watchdog monitor.

Auxiliary subsystem interfaces navigation subsystem, PLL and PMU subsystems.

PMU subsystem containing voltage regulators for RF and baseband domains.

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