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Multi Spider - ORG4572 Datasheet

Revision 3.0

November 23, 2014

12.2. ARCHITECTURE

1PPS

BB Power

RF Power

UART / SPI /I2C

RTC

TCXO

POR

LNA

GPS

Search / Track

Correlator

Engine

Sample

RAM

Embedded

Processor

Subsystem

ROM / RAM

SAW Filter

ON OFF

RESET

WAKEUP

Power

Management

HOST

VCC = 1.8V

RF in

SiRFstarV™ 5e GNSS SoC

LNA

FIGURE 1 – ORG4572 STANDARD ARCHITECTURE

GNSS SAW Filter

Band-Pass SAW filter eliminates out-of-band signals that may interfere to GNSS reception.

GNSS SAW filter is optimized for low insertion-loss in GNSS band and low return-loss outside it.

GNSS LNA

The integrated LNAs amplifies the GNSS signal to meet RF down converter input threshold.

Noise Figure optimized design was implemented to provide maximum sensitivity.

TCXO

Highly stable 26 MHz oscillator controls the down conversion process in RF block of the GNSS SoC.

Characteristics of this component are important factors for higher sensitivity, shorter TTFF and better

navigation stability.

RTC crystal

Tuning fork quartz crystal with very tight specifications is necessary for maintaining Hot Start and

Warm Start capabilities of the module.

RF Shield

RF enclosure avoids external interference from compromising sensitive circuitry inside the module.

RF shield also blocks module’s internal high frequency emissions from being radiated.

SiRFstarV™ 5e GNSS SoC

CSR 5e is a 5-th generation SiRFstar™ product.

It is a hybrid positioning processor that combines GPS, GLONASS, SBAS and MEMS sensor data to

provide a high performance navigation solution.

SiRFstarV™ 5e is a full SoC built on a low-power RF CMOS single-die, incorporating GNSS RF, GNSS

baseband, integrated navigation solution software and ARM® processor.