AP64100Q

Document number: DS43575 Rev. 1 - 2

14 of 26

www.diodes.com

July 2021

© Diodes Incorporated

AP64100Q

Application Information (continued)

10

Setting the Output Voltage

The AP64100Q has adjustable output voltages, starting from 0.8V, using an external resistive divider. The resistor values of the feedback network

are selected based on a design trade-off between efficiency and output voltage accuracy. There is less current consumption in the feedback

network for high resistor values, which improves efficiency at light loads. However, values too high cause the device to be more susceptible to

noise affecting its output voltage accuracy. R1 can be determined by the following equation:

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������������������������

������. ������������

− ������)

Eq. 6

Table 1 shows a list of recommended component selections for common AP64100Q output voltages referencing Figure 1.

Table 1. Recommended Components Selections, fSW = 500kHz

AP64100Q

Output Voltage

(V)

R1

(k

Ω)

R2

(k

Ω)

L

(µH)

C1

(µF)

C2

(µF)

C3

(nF)

C4

(pF)

R5

(kΩ)

C5

(nF)

C6

(pF)

1.2

4.99

10

6.8

2 x 10

22

100

OPEN

1.69

10

OPEN

1.5

8.66

10

8.2

2 x 10

22

100

OPEN

2.10

10

OPEN

1.8

12.40

10

10.0

2 x 10

22

100

OPEN

2.55

10

OPEN

2.5

21.50

10

10.0

2 x 10

22

100

OPEN

3.48

10

OPEN

3.3

31.60

10

15.0

2 x 10

22

100

OPEN

4.64

10

OPEN

5.0

52.30

10

15.0

2 x 10

22

100

OPEN

6.98

10

OPEN

12.0

140.00

10

33.0

2 x 10

22

100

OPEN

11.3

10

OPEN

11

Adjusting Switching Frequency

The switching frequency of the AP64100Q can be set through either of two modes, Resistor Timing or External Clock Synchronization.

In Resistor Timing mode, a resistor is placed between the RT/CLK pin to ground and sets the switching frequency over a wide range from 100kHz

to 2.2MHz. The RT/CLK pin voltage is typically 0.5V. The RT/CLK pin cannot be left floating. The RT resistance required for a given switching

frequency is calculated by:

������������[������������] =

������������������������������������

������������������[������������������]

Eq. 7

Where:



RT is the resistance in kΩ



fSW is the switching frequency in kHz between 100kHz to 2.2MHz

FSS is enabled when setting the switching frequency through Resistor Timing mode.

In External Clock Synchronization mode, the switching frequency synchronizes to an external clock applied to the RT/CLK pin. The

synchronization frequency range is also 100kHz to 2.2MHz, and the rising edge of SW synchronizes to the falling edge of the external clock at the

RT/CLK pin with a typical 66ns delay. An internal PLL locks the internal switching frequency to that of the external clock signal. An external square

wave clock signal supplied at the RT/CLK pin must have a logic high level greater than 3.5V, a logic low level less than 0.4V, and a pulse width of

at least 80ns.

FSS is disabled when setting the switching frequency through External Clock Synchronization mode.