| 전자부품 데이터시트 검색엔진 |
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AP64100Q 데이터시트(PDF) 23 Page - Diodes Incorporated |
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AP64100Q 데이터시트(HTML) 23 Page - Diodes Incorporated |
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23 / 26 page ![]() AP64100Q Document number: DS43575 Rev. 1 - 2 23 of 26 www.diodes.com July 2021 © Diodes Incorporated AP64100Q Layout PCB Layout 1. The AP64100Q works at 1A load current so heat dissipation is a major concern in the layout of the PCB. 2oz copper for both the top and bottom layers is recommended. 2. Place the input capacitors as closely across VIN and GND as possible. 3. Place the inductor as close to SW as possible. 4. Place the output capacitors as close to GND as possible. 5. Place the feedback components as close to FB as possible. 6. If using four or more layers, use at least the 2nd and 3rd layers as GND to maximize thermal performance. 7. Add as many vias as possible around both the GND pin and under the GND plane for heat dissipation to all the GND layers. 8. Add as many vias as possible around both the VIN pin and under the VIN plane for heat dissipation to all the VIN layers. 9. See Figure 34 for more details. C5 EXPOSED PAD BST VIN EN RT/CLK FB COMP GND SW C2 C3 R1 R2 R5 RT VOUT GND SW VIN Figure 34. Recommended PCB Layout |
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