AP64100Q

Document number: DS43575 Rev. 1 - 2

16 of 26

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AP64100Q

Application Information (continued)

13

Input Capacitor

The input capacitor reduces both the surge current drawn from the input supply as well as the switching noise from the device. The input capacitor

must sustain the ripple current produced during the on-time of Q1. It must have a low ESR to minimize power dissipation due to the RMS input

current.

The RMS current rating of the input capacitor is a critical parameter and must be higher than the RMS input current. As a rule of thumb, select an

input capacitor with an RMS current rating greater than half of the maximum load current.

Due to large dI/dt through the input capacitor, electrolytic or ceramic capacitors with low ESR should be used. If using a tantalum capacitor, it must

be surge protected or else capacitor failure could occur. Using a ceramic capacitor of 20µF or greater is sufficient for most applications.

14

Output Capacitor

The output capacitor keeps the output voltage ripple small, ensures feedback loop stability, and reduces both the overshoots and undershoots of

the output voltage during load transients. During the first few microseconds of an increasing load transient, the converter recognizes the change

from steady-state and enters 100% duty cycle to supply more current to the load. However, the inductor limits the change to increasing current

depending on its inductance. Therefore, the output capacitor supplies the difference in current to the load during this time. Likewise, during the first

few microseconds of a decreasing load transient, the converter recognizes the change from steady-state and sets the on-time to minimum to

reduce the current supplied to the load. However, the inductor limits the change in decreasing current as well. Therefore, the output capacitor

absorbs the excess current from the inductor during this time.

The effective output capacitance, COUT, requirements can be calculated from the equations below.

The ESR of the output capacitor dominates the output voltage ripple. The amount of ripple can be calculated by:

������������������������������������������������������������ = ∆������������ ∙ (������������������ +

������

������ ∙ ������������������ ∙ ������������������������

)

Eq. 10

Output capacitors with large capacitance and low ESR are the best option. For most applications, a total capacitance of 22µF using ceramic

capacitors is sufficient. To meet the load transient requirements, the calculated COUT should satisfy the following inequality:

������������������������ > ������������������ (

������ ∙ ������������������������������������

������

∆������������������������������������������������������������ ∙ ������������������������

,

������ ∙ ������������������������������������

������

∆������������������������������������������������������������������ ∙ (������������������ − ������������������������)

)

Eq. 11

Where:



ITrans is the load transient



∆VOvershoot is the maximum output overshoot voltage



∆VUndershoot is the maximum output undershoot voltage

15

Bootstrap Capacitor and Low-Dropout (LDO) Operation

To ensure proper operation, a ceramic capacitor must be connected between the BST and SW pins to supply the drive voltage for the high-side

power MOSFET. A 100nF ceramic capacitor is sufficient. If the bootstrap capacitor voltage falls below 2.3V, the boot undervoltage protection

circuit turns Q2 on for 300ns to refresh the bootstrap capacitor and raise its voltage back above 2.55V. The bootstrap capacitor threshold voltage

is always maintained to ensure enough driving capability for Q1. This operation may arise during long periods of no switching such as in PFM with

light load conditions. Another event that requires the refreshing of the bootstrap capacitor is when the input voltage drops close to the output

voltage. Under this condition, the regulator enters low-dropout mode by holding Q1 on for multiple clock cycles. To prevent the bootstrap capacitor

from discharging, Q2 is forced to refresh. The effective duty cycle is approximately 100% so that it acts as an LDO to maintain the output voltage

regulation.