FT800Q-R datasheet(28/46 Pages) BRIDGETEK

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FT800 Embedded Video Engine Datasheet

Version 1.4

Document No.: BRT_000039 Clearance No.: BRT#001

4.8.3.5 Wake up to ACTIVE from other power states

Wake up from POWERDOWN state requires the host to pull the PD_N pin down and release, a low to high

transition enables the 1.2V regulator. POR generated when 1.2V is stable and FT800 will switch to

STANDBY mode after internal oscillator and PLL are up (maximum 20ms from PD_N rising edge). The

clock enable sequence mentioned in section 4.2.3 shall be executed to proper enable the system clock.

From SLEEP state, host MPU reads at memory address 0 to wake the FT800 into ACTIVE state. Host

needs to wait for at least 20ms before accessing any registers or commands. This is to guarantee the

crystal oscillator and PLL are up and stable.

From STANDBY state, host MPU reads at memory address 0 to wake the FT800 into ACTIVE state. Host

can immediately access any register or command.

4.8.3.6 Pin Status at Different Power States

The FT800 pin status depends on the power state of the chip. See the following table for more details. At

power transition from ACTIVE to STANDBY or ACTIVE to SLEEP, all pins retains their previous status. The

software needs to set AUDIO_L, BACKLIGHT and PCLK to a known state before issuing power transition

commands.

Name

Reset State

(VCC / VCCIO

ON)

Reset State

(VCC / VCCIO ON)

Default Output Drive

Strength

Active/Sta

ndby/Sleep

state (VCC

/ VCCIO

ON)

Power down

state (VCC

ON / VCC1.2

OFF)

Hybrid Mode

(VCC OFF /

VCCIO ON)

AUDIO_L

Tristate Output

(hi-Z)

16mA

Output

Retain

previous state

SPI_SCL

K/I2C_S

Input (floating)

Input

Input (floating)

MISO/I2

C_SDA

Tristate Output

(hi-Z)

4mA

Input/output

Tristate Output

(hi-Z)

MOSI/I2

C_SA0

Input (floating)

Input

Input (floating)

CS_N/I2

C_SA1

Input (floating)

Input

Input (floating)

GPIO0/I2

C_SA2

Input (floating)

Input/output

Tristate Output

(hi-Z)

GPIO1

Tristate Output

(hi-Z)

4mA

Input/output

Tristate Output

(hi-Z)

MODE

Input

Input (floating)

INT_N

Open Drain

Output (hi-Z)

4mA

Open Drain

Output

Tristate Output

(hi-Z)

PD_N

Input

Input (floating)

X1/CLK

Input (floating)

Crystal

Oscillator

Input CLK

Input

Note: If

applicable,

external clock

on X1/CLK pin

should be

removed

Output (hi-Z)

Crystal

Oscillator

Output

X+

Tristate Output

(hi-Z)

Input/output

Retain

Previous State

Y+

Tristate Output

(hi-Z)

Input/output

Retain

Previous State

X-

Tristate Output

(hi-Z)

Input/output

Retain

Previous State

Y-

Tristate Output

(hi-Z)

Input/output

Retain

Previous State

BACKLIG

Output

4mA

Output

Retain

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