24LC08

8K-Bit Serial EEPROM

* All specs and applications shown above subject to change without prior notice.

1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU ,

TAOYUAN, TAIWAN

Email: server@ceramate.com.tw

Tel:886-3-3214525

Http: www.ceramate.com.tw

Fax:886-3-3521052

Page 5 of 23

Rev 1.1 Nov.18, 2002

FUNCTION DESCRIPTION

I

The 24LC08 supports the I

a serial data line (SDA) and a serial clock line (SCL). The SDA and the SCL lines must be connected to

Any device that puts data onto the bus is defined as the “transmitter” and any device that gets data from the bus

is the “receiver.” The bus is controlled by a master device which generates the serial clock and start/stop

conditions, controlling bus access. Using the A0,A1 and A2 input pins, up to two 24LC08 devices can be

connected to the same I

or receiver, but the master device determines which bus operating mode would be active.

SDA

Bus Master

(Transmitter/

Receiver)

MCU

24LC08

Tx/Rx

A0 A1 A2

Slave 1

24LC08

Tx/Rx

A0 A1 A2

Slave 2

R

R

SCL

Figure 3-6. Typical Configuration (16 Kbits of Memory on the I

NOTES:

1. The A0, A1 do not affect the device address of the 24LC08.