MCP960X datasheet(21/57 Pages) MICROCHIP

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DS20005426G-page 21

MCP960X/L0X/RL0X

4.1.5

DATA VALID

After the Start condition, each bit of data in

transmission needs to be settled for a time specified by

tSU-DATA before SCL toggles from low-to-high (see the

“Sensor Serial Interface Timing Specifications”

section).

4.1.6

ACKNOWLEDGE (ACK/NAK)

Each receiving device, when addressed, is expected to

generate an ACK bit after the reception of each byte.

The host device must generate an extra clock pulse for

ACK to be recognized.

The Acknowledging device pulls down the SDA line for

tSU-DATA before the low-to-high transition of SCL from

the host. SDA also needs to remain pulled down for

tHD-DAT after a high-to-low transition of SCL.

During read, the host must signal an End-of-Data

(EOD) to the device by not generating an ACK bit

(NAK) once the last bit has been clocked out of the

device. In this case, the device will leave the data line

released to enable the host to generate the Stop condi-

tion.

4.1.7

CLOCK STRETCHING

During the I2C read operation, this device will hold the

I2C clock line low for tSTRECH after the falling edge of

the ACK signal. In order to prevent bus contention, the

host controller must release or hold the SCL line low

during this period.

In addition, the host controller must provide eight con-

secutive clock cycles after generating the ACK bit from

a read command. This allows the device to push out

data from the SDA Output Shift registers. Missing clock

cycles could result in bus contention. At the end of one

or more data transmission, the host controller must pro-

vide the NAK bit, followed by a Stop Condition to

terminate communication (see Figure 4-3).

FIGURE 4-2:

Clock Stretching.

4.1.8

SEQUENTIAL READ

During a sequential read, the device transmits data

bytes starting from the previously set Register Pointer.

The MCP960X/L0X/RL0X increments an internal

address pointer each time a byte transmission is suc-

cessfully completed with an ACK bit from the host con-

troller. Therefore, the device can sequentially output

the entire register values shown in Table 5-1 (see

Figure 4-6). A Stop Condition terminates the sequential

read.

Note:

If the host controller does not provide the

adequate delay as specified by tSTRECH,

then the device will output the previously

transmitted data.

Note:

The

MCP960X/L0X/RL0X

does

not

support Sequential Write function.

2345

MCP960X/L0X/RL0X

Host

MCP960X/L0X/RL0X Clock Stretching – tSTRETCH

TH MSB Data

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