ADV7321 datasheet(45/88 Pages) AD

45 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 45 of 88

RESET SEQUENCE

A reset is activated with a high-to-low transition on the RESET

pin (Pin 33) according to the timing specifications, and the

ADV7320/ADV7321 reverts to the default output

configuration. Figure 63 illustrates the RESET timing sequence.

SD VCR FF/RW SYNC

[Subaddress 0x42, Bit 5]

In DVD record applications where the encoder is used with a

decoder, the VCR FF/RW sync control bit can be used for

nonstandard input video, i.e., in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new

field in the incoming video usually occurs before the correct

number of lines/fields are reached; in rewind mode, this sync

signal usually occurs after the total number of lines/fields are

reached. Conventionally this means that the output video will

have corrupted field signals, because one signal is generated by

the incoming video and another is generated when the internal

lines/field counters reach the end of a field.

When the VCR FF/RW sync control is enabled [Subaddress 0x42,

Bit 5], the lines/fields counters are updated according to the

incoming VSYNC signal, and the analog output matches the

incoming VSYNC signal.

This control is available in all slave timing modes except Slave

Mode 0.

XXXXXX

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

VALID VIDEO

TIMING ACTIVE

RESET

DIGITAL TIMING

DACs

A, B, C

PIXEL DATA

VALID

Figure 63. RESET Timing Sequence

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