ADV7321 datasheet(25/88 Pages) AD

25 / 88 page

ADV7320/ADV7321

Rev. 0 | Page 25 of 88

The MPU can write to or read from all registers of the

ADV7320/ADV7321 except the subaddress registers, which are

write only registers. The subaddress register determines which

communication with the part through the bus starts with an

access to the subaddress register. A read/write operation is then

performed from/to the target address, which increments to the

next address until a stop command is performed on the bus.

The following tables describe the functionality of each register.

All registers can be read from as well as written to, unless

otherwise stated.

SUBADDRESS REGISTER (SR7 TO SR0)

The communication register is an 8-bit write only register. After

the encoder’s bus is accessed and a read/write operation is

selected, the subaddress is set up. The subaddress register

determines to or from which register the operation takes place.

Table 7. Registers 0x00 to 0x01

SR7–

SR0

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reg. Reset

Values

(Shaded)

Sleep mode off.

0xFC

Sleep Mode. With this

control enabled, the

current consumption is

reduced to µA level. All

DACs and the internal PLL

cct are disabled. I2C

registers can be read from

and written to in sleep

mode.

Sleep mode on.

PLL on.

PLL and Oversampling

Control. This control

allows the internal PLL cct

to be powered down and

the oversampling to be

switched off.

PLL off.

DAC F off.

DAC F: Power On/Off.

DAC F on.

DAC E off.

DAC E: Power On/Off.

DAC E on.

DAC D off.

DAC D: Power On/Off.

DAC D on.

DAC C off.

DAC C: Power On/Off.

DAC C on.

DAC B off.

DAC B: Power On/Off.

DAC B on.

DAC A off.

0x00

Power

Mode

DAC A: Power On/Off.

DAC A on.

Reserved.

Cb clocked upon rising

edge.

Clock Edge.

Y clocked upon rising

edge.

Only for PS

interleaved

input at 27 MHz.

Reserved.

Clock Align.

Must be set if the phase

delay between the two

input clocks is <9.25 ns

or >27.75 ns.

Only if two

input clocks are

used.

SD input only.

0x38

PS input only.

HDTV input only.

SD and PS (20-bit).

SD and PS (10-bit).

SD and HDTV (SD

oversampled).

SD and HDTV (HDTV

oversampled).

Input Mode.

PS only (at 54 MHz).

0x01

Mode

Select

Y/C/S Bus Swap.

Allows data to be

applied to data ports in

various configurations

(SD feature only).

See Table 21.

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