4.1

Start condition

Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start

condition must precede any data transfer instruction. The device continuously monitors (except during a write

cycle) serial data (SDA) and serial clock (SCL) for a start condition.

4.2

Stop condition

Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A stop

condition terminates communication between the device and the bus master. A read instruction that is followed by

NoAck can be followed by a stop condition to force the device into the standby mode.

A stop condition at the end of a write instruction triggers the internal write cycle.

4.3

Data input

During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct

device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data

(SDA) signal must change only when serial clock (SCL) is driven low.

4.4

Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master

or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the

receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits.

M24M02-DR M24M02-R

Start condition

DS7025 - Rev 11

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