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SW52212 데이터시트(PDF) 59 Page - Silicon Laboratories

부품명 SW52212
상세설명  12/8/4/2-Output PCI-Express Gen 1/2/3/4/5 and SRIS Clock Generator
PDF  71 Pages
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제조업체  SILABS [Silicon Laboratories]
홈페이지  http://www.silabs.com
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10.4 Si52208 Land Pattern
The figure below illustrates the land pattern details for the Si52208 in a 48-Lead, 6 x 6 mm QFN package. The table lists the values for
the dimensions shown in the illustration.
Figure 10.4. 48L 6 x 6 mm QFN Land Pattern
Table 10.4. PCB Land Pattern Dimensions
Dimension
mm
C1
5.90
C2
5.90
X1
0.20
X2
3.60
Y1
0.85
Y2
3.60
e
0.40 BSC
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 mm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 3x3 array of 0.90 mm square openings on 1.15mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Data Sheet
Packaging
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