SW52212 datasheet(23/71 Pages) SILABS

23 / 71 page

5.6 PWRDNb (Power Down) Assertion

The PWRDNb pin is an asynchronous active low input used to disable all output clocks in a glitch-free manner. In power down mode, all

outputs, the crystal oscillator, and the I2C logic are disabled. In cases where the REF PWRDN (Byte 2, bit 2) is set to 1, the crystal

oscillator and REF output will still be enabled. All disabled outputs will be driven low.

Figure 5.5. PWRDNb Assertion

5.7 PWRDNb (Power Down) Deassertion

When a valid rising edge on PWRGD/PWRDNb pin is applied, all outputs are enabled in a glitch-free manner within 520 µs.

Figure 5.6. Subsequent Deassertion of PWRDNb

5.8 OEb Pin

The OEb pin is an active low input used to enable and disable the output clock. To enable the output clock, the OEb pin needs to be

logic low, and I2C OE bit needs to be logic high. By default, the OEb pin is set to logic low, and I2C OE bit is set to logic high.There are

two methods to disable the output clock: the OEb pin is pulled to a logic high, or the I2C OE bit is set to a logic low. This pin has a 100

kΩ internal pull-down.

5.9 OEb Assertion

The OEb pin is an active low input used for synchronous stopping and starting the respective output clock while the rest of the clock

generator continues to function. The assertion of the OEb function is achieved by pulling the OEb pin low while the I2C OE bit is high,

which causes the respective stopped output to resume normal operation. No short or stretched clock pulses are produced when the

clocks resume.

Data Sheet

Functional Description

silabs.com | Building a more connected world.

Rev. 1.0 | 23

SW52212 데이터시트(PDF) 23 Page - Silicon Laboratories