HC705P6AGRSSLASHD datasheet(25/134 Pages) NXP

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General Release Specification

Input/Output and Control Registers

MC68HC705P6A — Rev. 1.0

General Release Specification

Memory

2.5 Input/Output and Control Registers

Figure 2-2 and Figure 2-3 briefly describe the I/O and control registers

at locations $0000–$001F. Reading unimplemented bits will return

unknown states, and writing unimplemented bits will be ignored.

Figure 2-2. MC68HC705P6A I/O and Control Registers Memory Map

Port A Data Register

$0000

Port B Data Register

$0001

Port C Data Register

$0002

Port D Data Register

$0003

Port A Data Direction Register

$0004

Port B Data Direction Register

$0005

Port C Data Direction Register

$0006

Port D Data Direction Register

$0007

Unimplemented

$0008

Unimplemented

$0009

SIOP Control Register

$000A

SIOP Status Register

$000B

SIOP Data Register

$000C

Reserved

$000D

Unimplemented

$000E

Unimplemented

$000F

Unimplemented

$0010

Unimplemented

$0011

Timer Control Register

$0012

Timer Status Register

$0013

Input Capture MSB

$0014

Input Capture LSB

$0015

Output Compare MSB

$0016

Output Compare LSB

$0017

Timer MSB

$0018

Timer LSB

$0019

Alternate Counter MSB

$001A

Alternate Counter LSB

$001B

EPROM Programming Register

$001C

A/D Converter Data Register

$001D

A/D Converter Control & Status Reg

$001E

Reserved

$001F

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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