HC705P6AGRSSLASHD datasheet(82/134 Pages) NXP

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Analog Subsystem

General Release Specification

MC68HC705P6A — Rev. 1.0

Analog Subsystem

9.7 A/D Conversion Data Register (ADC)

This register contains the output of the A/D converter. See Figure 9-2.

9.8 A/D Subsystem Operation during Halt/Wait Modes

The A/D subsystem continues normal operation during wait and halt

modes. To decrease power consumption during wait or halt mode, the

ADON and ADRC bits in the A/D status and control register should be

cleared if the A/D subsystem is not being used.

9.9 A/D Subsystem Operation during Stop Mode

When stop mode is enabled, execution of the STOP instruction will

terminate all A/D subsystem functions. Any pending conversion is

aborted. When the oscillator resumes operation upon leaving stop

mode, a finite amount of time passes before the A/D subsystem

stabilizes sufficiently to provide conversions at its rated accuracy. The

delays built into the MC68HC705P6A when coming out of stop mode are

sufficient for this purpose. No explicit delays need to be added to the

application software.

$001D

Bit 7

654321

Bit 0

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

Unaffected by reset

= Unimplemented

Figure 9-2. A/D Conversion Value Data Register (ADC)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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