HC705P6AGRSSLASHD datasheet(80/134 Pages) NXP

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Analog Subsystem

General Release Specification

MC68HC705P6A — Rev. 1.0

Analog Subsystem

9.6 A/D Status and Control Register (ADSC)

The ADSC register reports the completion of A/D conversion and

provides control over oscillator selection, analog subsystem power, and

input channel selection. See Figure 9-1.

CC — Conversion Complete

This read-only status bit is set when a conversion sequence has

completed and data is ready to be read from the ADC register. CC is

cleared when the ADSC is written to or when data is read from the

ADC register. Once a conversion has been started, conversions of

the selected channel will continue every 32 internal clock cycles until

the ADSC register is written to again. During continuous conversion

operation, the ADC register will be updated with new data, and the CC

bit set every 32 internal clock cycles. Also, data from the previous

conversion will be overwritten regardless of the state of the CC bit.

ADRC — RC Oscillator Control

When ADRC is set, the A/D subsystem operates from the internal RC

oscillator instead of the internal clock. The RC oscillator requires a

time, tRCON, to stabilize before accurate conversion results can be

obtained. See 9.3.2 Reference Voltage (VREFH) for more

information.

ADON — A/D Subsystem On

When the A/D subsystem is turned on (ADON = 1), it requires a time,

tADON, to stabilize before accurate conversion results can be attained.

$001E

Bit 7

654321

Bit 0

Read:

ADRC

ADON

CH2

CH1

CH0

Write:

Reset:

00000000

= Unimplemented

Figure 9-1. A/D Status and Control Register (ADSC)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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