STM32U595AI datasheet(257/377 Pages) STMICROELECTRONICS

257 / 377 page

DS13633 Rev 1

257/377

STM32U59xxx

Electrical characteristics

343

Static latch-up

The following complementary static tests are required on three parts to assess the latch-up

performance:

•

A supply overvoltage is applied to each power supply pin.

•

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78E IC latch-up standard.

5.3.13

I/O current injection characteristics

As a general rule, the current injection to the I/O pins, due to external voltage below VSS or

above VDDIOx (for standard, 3.3 V-capable I/O pins) must be avoided during normal product

operation. However, in order to give an indication of the robustness of the microcontroller if

abnormal injection accidentally happens, some susceptibility tests are performed on a

sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating-input mode. While this current is injected

into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter, such as an ADC error above a certain

limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on

adjacent pins (out of the -5 µA/+0 µA range), or other functional failure (for example reset

occurrence or oscillator frequency deviation).

Table 82. Electrical sensitivities(1)

Symbol

Parameter

Conditions

Class

Static latch-up class

TJ = 130 °C conforming to JESD78E

Class II level A

1. Evaluated by characterization. Not tested in production.

STM32U595AI 데이터시트(PDF) 257 Page - STMicroelectronics