STM32U595AI datasheet(297/377 Pages) STMICROELECTRONICS

297 / 377 page

DS13633 Rev 1

297/377

STM32U59xxx

Electrical characteristics

343

Figure 47. MDF timing diagram

5.3.29

DCMI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature, fHCLK frequency and VDD supply voltage

summarized in Table 32, with the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

DCMI_PIXCLK polarity: falling

•

DCMI_VSYNC and DCMI_HSYNC polarity: high

•

Data formats: 14 bits

•

Capacitive load CL = 30 pF

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1

MSv69125V1

MDF_SDIx (I)

MDF_CKIx (I)

MDF_CCK (I/O)

tSUCKI

tSUCCKI

tSUCCKO

tSUCCKOLF

fCKI, fCCKI, FCCKO, fCCKOLF

tLCKI, tLCCKI,

tLCCKO

tHDCKI

tHDCCKI

tHDCCKO

tHDCCKOLF

tHCKI, tHCCKI,

tHCCKO

tSUCKI

tSUCCKI

tSUCCKO

tSUCCKOLF

tHDCKI

tHDCCKI

tHDCCKO

tHDCCKOLF

Table 111. DCMI characteristics(1)

1. Evaluated by characterization. Not tested in production.

Symbol

Parameter

Min

Max

Unit

Frequency ratio DCMI_PIXCLK/fHCLK

-0.4

DCMI_PIXCLK

Pixel clock input

MHz

DPIXEL

Pixel clock input duty cycle

tsu(DATA)

Data input setup time

2.5

th(DATA)

Data hold time

tsu(HSYNC)

tsu(VSYNC)

DCMI_HSYNC and DCMI_VSYNC input setup times

th(HSYNC)

th(VSYNC)

DCMI_HSYNC and DCMI_VSYNC input hold times

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