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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32U595AI 데이터시트(PDF) 298 Page - STMicroelectronics |
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STM32U595AI 데이터시트(HTML) 298 Page - STMicroelectronics |
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298 / 377 page  Electrical characteristics STM32U59xxx 298/377 DS13633 Rev 1 Figure 48. DCMI timing diagram 5.3.30 PSSI characteristics Unless otherwise specified, the parameters given in the table below are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 32, with the following configuration: • Output speed set to OSPEEDRy[1:0] = 10 • PSSI_PDCK polarity: falling • PSSI_RDY and PSSI_DE polarity: low • Bus width: 16 lines • Data width: 32 bits • Capacitive load CL = 30 pF • Measurement points done at 0.5 × VDD level • I/O compensation cell activated • HSLV activated when VDD ≤ 2.7 V • Voltage scaling range 1 MS32414V2 DCMI_PIXCLK tsu(VSYNC) tsu(HSYNC) DCMI_HSYNC DCMI_VSYNC DATA[0:13] 1/DCMI_PIXCLK th(HSYNC) th(HSYNC) tsu(DATA) th(DATA) Table 112. PSSI transmit characteristics(1) Symbol Parameter Conditions Min Max Unit - Frequency ratio DCMI_PDCK/fHCLK -- 0.4 - PSSI_PDCK PSSI clock input 2.7 V ≤ VDD ≤ 3.6 V - 64(2) MHz 1.71 V ≤ VDD ≤ 3.6 V - 47(2) DPIXEL PSSI clock input duty cycle - 30 70 % |
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