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STM32U595AI 데이터시트(PDF) 317 Page - STMicroelectronics |
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STM32U595AI 데이터시트(HTML) 317 Page - STMicroelectronics |
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317 / 377 page ![]() DS13633 Rev 1 317/377 STM32U59xxx Electrical characteristics 343 Figure 60. Synchronous multiplexed PSRAM write timings td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 1.5 ns td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tHCLK + 1 - td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 2 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 4 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 1 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 - 1. Evaluated by characterization. Not tested in production. 2. Clock ratio R = (HCLK period /FMC_CLK period). Table 131. Synchronous multiplexed NOR/PSRAM read timings(1)(2) (continued) Symbol Parameter Min Max Unit |
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