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STM32U595AI 데이터시트(PDF) 321 Page - STMicroelectronics |
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STM32U595AI 데이터시트(HTML) 321 Page - STMicroelectronics |
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321 / 377 page ![]() DS13633 Rev 1 321/377 STM32U59xxx Electrical characteristics 343 NAND controller waveforms and timings Figure 63 to Figure 66 represent synchronous waveforms, and Table 135/Table 136 provide the corresponding timings. The results shown in these tables are obtained with the following FMC configuration: • COM.FMC_SetupTime = 0x01 • COM.FMC_WaitSetupTime = 0x03 • COM.FMC_HoldSetupTime = 0x02 • COM.FMC_HiZSetupTime = 0x01 • ATT.FMC_SetupTime = 0x01 • ATT.FMC_WaitSetupTime = 0x03 • ATT.FMC_HoldSetupTime = 0x02 • ATT.FMC_HiZSetupTime = 0x01 • Bank = FMC_Bank_NAND • MemoryDataWidth = FMC_MemoryDataWidth_16b • ECC = FMC_ECC_Enable • ECCPageSize = FMC_ECCPageSize_512Bytes • TCLRSetupTime = 0 • TARSetupTime = 0 In all timing tables, the THCLK is the HCLK clock period. Figure 63. NAND controller waveforms for read access tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - ns th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 2.5 - 1. Evaluated by characterization. Not tested in production. Table 134. Synchronous non-multiplexed PSRAM write timings(1) (continued) Symbol Parameter Min Max Unit MSv38003V1 FMC_NWE FMC_NOE (NRE) FMC_D[15:0] tsu(D-NOE) th(NOE-D) ALE (FMC_A17) CLE (FMC_A16) FMC_NCEx td(NCE-NOE) th(NOE-ALE) |
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