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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STPM066S 데이터시트(PDF) 18 Page - STMicroelectronics |
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STPM066S 데이터시트(HTML) 18 Page - STMicroelectronics |
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18 / 67 page  Figure 5. SYNCOUT output buffer IC 3.3V inner supply SYNCOUT DGND SYNCOUT output buffer GADG1105180841PS 4.2.8 Reset and Fault In ACTIVE mode, a reset signal is generated by STPM066S at RESET_B pin in case of UV, OV if enabled by OTP, PG loss on BUCK regulator and Watchdog failure (wrong trigger of WD). Every regulator that can issue a reset, moves the device to REC state. Reset behavior at Power Up phase is fully described in Section 6 Device operating mode. Figure 6. Reset circuit diagram in ACTIVE mode ≥ 1 RESET_B pin Watchdog failure Buck_pg_loss Buck_mon_uv & RstEn Control Bits OTP user setup Ldo_mon_uv/ov Buck_mon_uv/ov/pg MUX GADG3105190937PS STPM066S Voltage regulators and features description DS12976 - Rev 2 page 18/67 |
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