STPM066S datasheet(19/67 Pages) STMICROELECTRONICS

19 / 67 page

A loss of ground (PGLOSS) asserts RESET_B with the following rules:

if the regulator is disabled by OTP, PGLOSS cannot assert RESET_B;

if the regulator is enabled by OTP, but it is not in the Reset Activation list, PGLOSS cannot assert RESET_B;

if the regulator is enabled by OTP and it is in the Reset Activation list, no matter if it is disabled by SPI,

PGLOSS can assert RESET_B.

The undervoltage (UV) asserts RESET_B with the following rules:

•

if the regulator is disabled by OTP, UV cannot assert RESET_B;

•

if the regulator is enabled by OTP, but it is not in the Reset Activation list, UV cannot assert RESET_B;

•

it the regulator is enabled by OTP and it is in the Reset Activation list, but it is disabled by SPI, UV cannot

assert RESET_B;

•

if the regulator is enabled by OTP, it is in the Reset Activation list, no matter if it is disabled by SPI, UV can

assert RESET_B.

The overvoltage (OV) asserts RESET_B in a similar way as the undervoltage, with this additional condition:

•

if OvRst_EN is set to 0 through OTP, the OV cannot assert RESET_B.

A FAULT signal is generated in active mode in case of a fault, as shown in Figure 7.

•

"SPI_parity_fail" refers to SPI_PAR_FAIL, Bit2 of SPI fault STAT

•

"PowerUp fault" is an error generated by regulators during power-up phase:

–

each regulator should complete its own power-up phase up to the power good signal within 20 ms

•

"Digital_Bist_err" is an error generated by one of the following checks:

–

Buck clock generation

–

Logic diagnostics circuit

–

Main State Machine

Figure 7. Fault function in active mode

NOR

FAULT pin

‘1’: no fault

‘0’: with fault

VBAT1/VBAT2_uv/ov

(read&clear)

Buck_fault

(read&clear)

Watchdog_fail

(read&clear)

SPI_fail

(read&clear)

LBIST_err

PowerUp_fault

Center1/2/3_ot

Vref_uv/ov/oc

Boost_uv/ov/oc/ot/pg_loss

Buck_uv/ov/oc/ot/pg_loss

GADG3105190950PS

LDO_uv/ov/ot

Center_ot

In order to avoid triggering RESET and FAULT during the soft start time, the UV is masked when regulators

(BUCK, BOOST, LDO and VREF) are going to be enabled. The masking time is given by the following table.

Table 7. UV masking time

Regulator

Masking time (ms typ.)

BUCK and BOOST

LDO and VREF

0.5

STPM066S

Voltage regulators and features description

DS12976 - Rev 2

page 19/67

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