STM32U545NET3QTR datasheet(205/283 Pages) STMICROELECTRONICS

205 / 283 page

DS14216 Rev 1

205/283

STM32U545xx

Electrical characteristics

258

Static latch-up

The following complementary static tests are required on three parts to assess the latch-up

performance:

•

A supply overvoltage is applied to each power supply pin.

•

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with EIA/JESD 78E IC latch-up standard.

5.3.13

I/O current injection characteristics

As a general rule, the current injection to the I/O pins, due to external voltage below VSS or

above VDDIOx (for standard, 3.3 V-capable I/O pins) must be avoided during normal product

operation. However, in order to give an indication of the robustness of the microcontroller if

abnormal injection accidentally happens, some susceptibility tests are performed on a

sample basis during the device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting

current into the I/O pins programmed in floating-input mode. While this current is injected

into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out-of-range parameter, such as an ADC error above a certain

limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on

adjacent pins (out of the -5 µA/+0 µA range), or other functional failure (for example reset

occurrence or oscillator frequency deviation).

The characterization results are given in the table below. The negative induced leakage

current is caused by the negative injection. The positive induced leakage current is caused

by the positive injection.

5.3.14

I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the conditions summarized in Table 33. All I/Os are designed as

CMOS- and TTL-compliant.

Table 92. I/O current injection susceptibility(1)(2)

Symbol

Description

Functional susceptibility

Unit

Negative injection

Positive injection

IINJ

Injected current on PA4 and PA5 pins

Injected current on other PA1, PA6, PA7, PB0,

and PB1 pins

0N/A

Injected current on all other pins

N/A

1. Evaluated by characterization. Not tested in production.

2. The I/O structure options listed in this table can be a concatenation of options including the option explicitly listed. For

instance TT_a refers to any TT I/O with _a option. TT_xx refers to any TT I/O and FT_xx refers to any FT I/O.

STM32U545NET3QTR 데이터시트(PDF) 205 Page - STMicroelectronics

STM32U545NET3QTR 데이터시트(HTML) 205 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL