List of figures

Figure 1.

Pin connections for each package (top view) ............................................... 2

Figure 2.

Supply current vs. supply voltage (per channel) ............................................ 10

Figure 3.

Supply current vs. input common mode voltage per channel (VCC = 36 V) .......................... 10

Figure 4.

Input offset voltage distribution, T = 25 °C VCC = 12 V ........................................ 10

Figure 5.

Input offset voltage temperature coefficient distribution from -40 °C to 25 °C (µV/°C), VCC = 12 V .......... 10

Figure 6.

Input offset voltage temperature coefficient distribution from 25 °C to 125 °C (µV/°C), VCC = 12 V .......... 11

Figure 7.

Input offset voltage vs. supply voltage ................................................... 11

Figure 8.

Input offset voltage vs. input common mode voltage VCC = 36 V ................................ 11

Figure 9.

Input bias current vs. temperature at mid VICM ............................................. 11

Figure 10.

Output voltage drop vs. output current load, VCC = 36 V, Vicm = VCC/2, Vid = -1 V for sink, +1 V for source .... 12

Figure 11.

High-level output voltage (drop from VCC+) vs. VCC, Iload = 160 mA ............................... 12

Figure 12.

High-level output voltage, (drop from VCC+) vs. temperature, Iload = 160 mA ......................... 12

Figure 13.

Low-level output voltage vs. VCC, Iload = 160 mA............................................ 12

Figure 14.

Low-level output voltage vs. temperature, Iload = 160 mA ...................................... 13

Figure 15.

Slew rate vs. Vcc, Rload = 10 kΩ, Cload = 100 pF, comparator mode, Vdiff = 5 V ....................... 13

Figure 16.

Small signal response at 36 V supply voltage .............................................. 13

Figure 17.

Bode Diagram, Vcc = 36 V, Rl = 10 kΩ, Cload = 100 pF, common mode voltage = 18 V .................. 13

Figure 18.

Unity gain frequency vs. temperature, VCC = 36 V, Rl = 10 kΩ................................... 14

Figure 19.

Phase margin vs. capacitive load VCC = 36 V, Rl = 10 kΩ ...................................... 14

Figure 20.

Gain margin vs. capacitive load VCC = 36 V, Rl = 10 kΩ ....................................... 14

Figure 21.

Overshoot vs. capacitive load ......................................................... 14

Figure 22.

Noise vs. frequency for different supply voltages ............................................ 15

Figure 23.

THD vs. Output voltage swing for different frequencies, VCC = 36 V, Rl = 10 kΩ, Cl = 100 pF ............. 15

Figure 24.

THD vs. frequency for different Vcm, VCC = 36 V, Vicm = Vocm = Vcm, Rl = 10 kΩ, Cl = 100 pF ............. 15

Figure 25.

PSRR vs. frequency ............................................................... 15

Figure 26.

Channel separation vs. frequency ...................................................... 16

Figure 27.

Equivalent internal ESD and input protection circuit .......................................... 17

Figure 28.

EMI rejection ratio vs. frequency ....................................................... 18

Figure 29.

SO8 safe operating area, one channel active .............................................. 19

Figure 30.

DFN8 safe operating area, one channel active ............................................. 19

Figure 31.

Stability criteria with a serial resistor at different capacitive loads................................. 20

Figure 32.

Test configuration for RISO ........................................................... 20

Figure 33.

Rotary resolver excitation amplifier ..................................................... 22

Figure 34.

Increasing output current ............................................................ 23

Figure 35.

SO8 exposed pad package outline ..................................................... 25

Figure 36.

SO8 exposed pad footprint data ....................................................... 26

Figure 37.

DFN8 3x3 exposed pad, wettable flank package outline and mechanical data........................ 27

Figure 38.

DFN8 3x3 exposed pad, wettable flank footprint data......................................... 28

TSB582

List of figures

DS13378 - Rev 2

page 33/34