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LSM6DS3TR-C 데이터시트(PDF) 38 Page - STMicroelectronics |
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LSM6DS3TR-C 데이터시트(HTML) 38 Page - STMicroelectronics |
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38 / 115 page ![]() Digital interfaces LSM6DS3TR-C 38/115 DocID030071 Rev 3 6 Digital interfaces 6.1 I2C/SPI interface The registers embedded inside the LSM6DS3TR-C may be accessed through both the I2C and SPI serial interfaces. The latter may be SW configured to operate either in 3-wire or 4- wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the CS line must be tied high (i.e connected to Vdd_IO). 6.2 Master I2C If the LSM6DS3TR-C is configured in Mode2, a master I2C line is available. The master serial interface is mapped in the following dedicated pins. Table 10. Serial interface pin description Pin name Pin description CS SPI enable I2C/SPI mode selection (1: SPI idle mode / I2C communication enabled; 0: SPI communication mode / I2C disabled) SCL/SPC I2C Serial Clock (SCL) SPI Serial Port Clock (SPC) SDA/SDI/SDO I2C Serial Data (SDA) SPI Serial Data Input (SDI) 3-wire Interface Serial Data Output (SDO) SDO/SA0 SPI Serial Data Output (SDO) I2C less significant bit of the device address Table 11. Master I2C pin details Pin name Pin description MSCL I2C serial clock master MSDA I2C serial data master MDRDY I2C master external synchronization signal |
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