SN250 datasheet(110/130 Pages) STMICROELECTRONICS

110 / 130 page

Functional description—application modules

SN250

110/130

Equation notes:

●

All N are 16-bit numbers.

●

NX is a sampling of the desired analog source.

●

NVSS is a sampling of ground. Due to the nature of the ADC’s internal design, ground

does not yield 0x0000 in the ADC_DATA register. Instead, ground yields a value closer

to 1/3 of the range — for example, 0x5200.

●

NVREF is a sampling of VREF. Due to the nature of the ADC’s internal design, VREF

does not yield 0xFFFF in the ADC_DATA register. Instead, VREF yields a value closer

to 2/3 of the range — for example, 0xA800.

●

NVDD is a sampling of the regulated supply, VDD/2.

●

<<16 indicates a bit shift left by 16 bits.

●

When calculating the voltage of VDD_PADS (ADC_SEL = 4), V = (1/4) * VDD_PADS

●

When calculating the voltage of VDD (ADC_SEL = 5), V = (1/2) * VDD

Table 36 lists the specifications for the ADC.

The signal-ended ADC measurements are limited in their range and only guaranteed for

accuracy in the range of 0 to VREF. The nature of the ADC’s internal design allows for

measurements outside of this range, but such measurements are not guaranteed and

instead act as a factor of safety. Maximum input voltage, VDD, can be treated as the failure

point. Measurement is not guaranteed at this level, and damage is possible above this level.

The maximum input voltage is of mor interest to the differential sampling where a differential

measurement might be small, but a common mode can push the actual input voltage on one

of the signals towards VDD.

Table 36.

ADC specifications

Parameter

Min.

Typ.

Max.

Unit

Conversion time

4096

μs

VREF

1.2

VREF output current

VREF load capacitance

Minimum input voltage

Maximum input voltage

VDD

Single-ended signal range

VREF

Differential signal range

- VREF

+ VREF

Common mode range

VREF

Input referred ADC offset

- 10

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