SN250 datasheet(47/130 Pages) STMICROELECTRONICS

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SN250

Functional description—application modules

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There are two schemes available to assert the RTS signal. The first scheme is to initiate

RTS assertion with software by setting the register bit SC1_UARTRTS in the SC1_UARTCFG

receive FIFO. This is enabled with the register bit SC1_UARTAUTO in the SC1_UARTCFG

The UART also contains overrun protection for both the FIFO and DMA options. If the

transmitting terminal continues to transmit characters to the receive FIFO, only 4 characters

are stored in the FIFO. Additional characters are dropped, and the register bit

SC1_UARTRXOVF

in the SC1_UARTSTAT register is set. Should this receive overrun occur

during DMA operation, the SC1_RXERRA/B registers mark the error-offset. The RX FIFO

hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate the

error condition until the RX FIFO is drained. Once the DMA marks a RX error, there are two

conditions that will clear the error indication: setting the appropriate SC_TX/RXDMARST bit in

the SC1_DMACTRL register, or loading the appropriate DMA buffer after it has unloaded.

Interrupts are generated on the following events:

●

Transmit FIFO empty and last character shifted out (0 to 1 transition of

SC1_UARTTXIDLE

)

●

Transmit FIFO changed from full to not full (0 to 1 transition of SC1_UARTTXFREE)

●

Receive FIFO changed from empty to not empty (0 to 1 transition of SC1_UARTRXVAL)

●

Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)

●

Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)

●

Character received with Parity error

●

Character received with Frame error

●

Received and lost character while receive FIFO was full (Receive overrun error)

To generate interrupts to the CPU, the interrupt masks in the INT_SC1CFG and INT_CFG

registers must be enabled.

7.2.2

SPI master mode

The SPI mode of the SC1 is master mode only. It has a fixed word length of 8 bits. The SC1

SPI controller is enabled with SC1_MODE set to 2 and register bit SC_SPIMST set in the

SC1_SPICFG

The SPI mode has the following features:

●

Full duplex operation

●

Programmable clock frequency (12MHz max.)

●

Programmable clock polarity and clock phase

●

Selectable data shift direction (either LSB or MSB first)

The following signals can be made available on the GPIO pins:

●

MO (master out)

●

MI (master in)

●

MCLK (serial clock)

The SC1 SPI module obtains its reference clock from a programmable clock generator.

Clock rates are set by a clock division ratio from the 24MHz clock:

rate = 24MHz / ( 2

∗ (LIN + 1) ∗ 2EXP )

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