SN250 datasheet(49/130 Pages) STMICROELECTRONICS

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SN250

Functional description—application modules

49/130

When a transmit character is written to the (empty) transmit FIFO, the register bit

SC_SPITXIDLE

in the SC1_SPISTAT register clears and indicates that not all characters

are transmitted yet. Further transmit characters can be written to the transmit FIFO until it is

full, which causes the register bit SC_SPITXFREE in the SC1_SPISTAT register to clear.

After shifting one transmit character to the MO pin, space for one transmit character

becomes available in the transmit FIFO. This causes the register bit SC_SPITXFREE in the

SC1_SPISTAT

empties, which causes the register bit SC_SPITXIDLE in the SC1_SPISTAT register to get

set also.

Any character received is stored in the (empty) receive FIFO. The register bit

SC_SPIRXVAL

in the SC1_SPISTAT register is set to indicate that not all received

characters are read out from receive FIFO. If software or DMA is not reading from the

receive FIFO, the receive FIFO will store up to 4 characters. Any further reception is

dropped and the register bit SC_SPIRXOVF in the SC1_SPISTAT register is set. The RX

FIFO hardware generates the INT_SCRXOVF interrupt, but the DMA register will not indicate

the error condition until the RX FIFO is drained. Once the DMA marks a RX error, there are

two conditions that will clear the error indication: setting the appropriate SC_TX/RXDMARST

bit in the SC1_DMACTRL register, or loading the appropriate DMA buffer after it has

unloaded.

Receiving a character always requires transmitting a character. In a case when a long

stream of receive characters is expected, a long sequence of (dummy) transmit characters

must be generated. To avoid software or transmit DMA initiating these transfers (and

consuming unnecessary bandwidth), the SPI serializer can be instructed to retransmit the

last transmitted character, or to transmit a busy token (0xFF), which is determined by the

(or disabled) when the transmit FIFO is empty and the transmit serializer is idle, as indicated

by a cleared SC_SPITXIDLE register bit in the SC1_SPISTAT register.

Every time an automatic character transmission is started, a transmit underrun is detected

(as there is no data in transmit FIFO), and the register bit INT_SCTXUND in the

INT_SC1FLAG

transmission, the reception of new characters stops and the receive FIFO holds characters

just received.

Note:

The event Receive DMA complete does not automatically mean receive FIFO empty.

Interrupts are generated on the following events:

●

Transmit FIFO empty and last character shifted out (0 to 1 transition of

SC_SPITXIDLE

)

●

Transmit FIFO changed from full to not full (0 to 1 transition of SC_SPITXFREE)

●

Receive FIFO changed from empty to not empty (0 to 1 transition of SC_SPIRXVAL)

●

Transmit DMA buffer A/B complete (1 to 0 transition of SC_TXACTA/B)

●

Receive DMA buffer A/B complete (1 to 0 transition of SC_RXACTA/B)

●

Received and lost character while receive FIFO was full (Receive overrun error)

●

Transmitted character while transmit FIFO was empty (Transmit underrun error)

To generate interrupts to the CPU, the interrupt masks in the INT_SC1CFG and INT_CFG

registers must be enabled.

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